Electronic Component Solutions

Video Frame/Data Buffering and Synchronization for 4K applications

See the case studies below and learn how you can manage them with AL462, 4K FIFO memory, and the video processors, AL362, AL361 and AL360.

World’s largest and fastest FIFO Memory Buffer for 4K2K UltraHD Video Applications

4K UHD Video Processor for Quad View, Multiple Display and TV Wall

UHD 4K2K Dual-channel Video Processor

SKU: 10045



  • Highly integrated single chip
    Embedded 8051 MCU, low power DDR, flash and video processing engine with small-size package LFBGA-249 12×12 mm.
  • Varietal video input/output interfaces
    Multi-channel video processing engine with SD, HD digital video combinations, such as 24-bit RGB, 16-bit YC and 8-bit YC inputs and outputs.
  • Video Processing
    Configurable flexi-port supports de-interlacing, cropping, scaling, OSD, format conversion, PIP and POP for 4K2K display.



  • Supports 64-bit 4-port Inputs and 2-port outputs with different video contents
  • Supports varieties of SD, HD video input combinations, such as dual 24-bit, quad 16-bit, quad 8-bit for video convert to designate video windows/switching plus alpha blending output with OSD
  • Supports digital RGB/YUV raw data, BT.656, BT.1120 input or 4x clock multiplexing data timing at maximum 150Mhz clock rate
  • Configurable Flexi-Port supports odd/even pixel and Double-Data-Rate (DDR) bus interface for industrial video ASIC, such as HDMI transmitter/receiver, solutions (no glue-logic required) in high resolution video design, such as UltraHD 4k2k applications
  • Supports window composition of multiple input videos, such as PiP, PoP and quad display for maximum 4k2k input/output resolution
  • Allows cropping/splitting input video as sub-window for multi-display outputs
  • Video processing engine supports varieties of video manipulations, such as D1 de-interlacing, timing base conversion, cropping, Image freeze
  • Supports Character (font), Icon-Based and 8-bit Bitmap OSD overlay
  • Embedded 8051 MCU and setup chip configuration via i2c bus
  • Supports SPI for firmware download
  • Cost effective, low power (1.8V core & 1.8V-3.3V I/O) in 249-pin Lead Free (PBF)
  • LFBGA package, small foot-print design principle



  • 512M-bits configurable to 32-bit or 16-bit x2 bus width FIFO (First-In-First-Out) memory
  • Independent input/output synchronous data access (different I/O data rates acceptable)
  • Supports one 16Mx32-bit or dual 16Mx16-bit organizations
  • High speed synchronous sequential access in Maximum 150Mhz clock rate
  • 9.6 GB/sec simultaneous R/W throughput
  • Supports input/output enable controls
  • Selectable control signal polarity
  • Gated Read clock Output
  • Supports 2-frame mode for double buffering
  • 1.8V/3.3V power supply
  • Standard 249-ball LFBGA package

Datasheet AL361 Datasheet AL362 Datasheet AL462

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