The current specification of each rail can vary depending upon the part number and specific application/program that will be running on the RFSoC. Table 1 illustrates the typical current requirement of each rail for the Zynq UltraScale+ RFSoC family. It is recommended to use the Xilinx Power Estimation (XPE) tool to estimate the accurate current requirement for optimization of the power solution design. Besides the voltage and current specifications, the power supplies for Xilinx FPGA power rails must meet the following requirements:
- The output voltage ripple of all power rails (except for analog rails) must be smaller than 10mV in steady state.
- The start-up of all power rails must be monotonic.
- Output voltage deviation of the core rail (VCCINT) must be smaller than +- 3% during a 25% load transient at 100A/μs.
- The turn-on and turn-off of the power supplies must follow a certain sequence defined by Xilinx.