DDR3 SDRAMs (2Gb & 4Gb) resistant against Rowhammer attacks

Zentel meets the demand for the digital industry for secure SDRAM-ICs. Since the introduction of the DDR3 JEDEC standard years ago a vulnerability of data integrity was enabling even OS-protected parts of DRAM to be corrupted by an exploit of a new DRAM hardware weakness called Row Hammer.

The new RowHammerfree DDR3 SDRAM-ICs are equipped with an integrated trapping circuit that would detect and block such attacks not affecting the overall performance or current consumption noticeably providing full DDR3 JEDEC compliance and footprint compatibility as drop-in replacement to conventional DDR3 SDRAM.

The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
Double data-rate architecture: two data transfers per clock cycle
Bi-directional differential data strobe (DQS and/DQS) is transmitted/received with data for capturing data at the receiver
DQS is edge-aligned with data for READs; center aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK transitions
Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
Data mask (DM) for write data
Posted CAS by programmable additive latency for better command and data bus efficiency
On-Die Termination (ODT) for better signal quality
– Synchronous ODT
– Dynamic ODT
– Asynchronous ODT
Multi Purpose Register (MPR) for pre-defined

DDR3 SDRAMs (2Gb & 4Gb) resistant against Rowhammer attacks

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